1. Field of the Invention
The present invention relates to an image processing apparatus, an image processing circuit, and an image processing method.
2. Description of the Related Art
In image encoding and decoding based on wavelet transform, various codes of information including transform coefficients are present in every level of sub-band decomposition. Some image processing apparatuses have been known that efficiently load these codes into memories and provide easy access to the codes.
For example, Japanese Patent Laid-Open Publication No. 2006-297485 (Patent Document 1) discloses an image processing apparatus that varies the size of memory space to be allocated for storing one unit of data according to the bit depth of the data, which data are created by at least one processing step, thereby improving memory utilization efficiency.
As another example, Japanese Patent Laid-Open Publication No. 2004-254298 (Patent Document 2) discloses an image processing apparatus that includes a distributed storage unit that stores compressed codes of different levels in a distributed fashion, thereby enabling high-speed processing.
In the encoding scheme of JPEG 2000, information items related to code-blocks, each including a set of transform coefficients, in different levels are encoded using a tree structure called a tag tree. In the tag tree structure, if a first code-block has the same parent code-block as a second code-block, the code for the tag level can be omitted in the second code-block, thereby enabling efficient encoding.
However, in encoding and decoding processes using such a tag tree structure, when processing one code-block, it is necessary to hold codes in all the tag levels from the immediately higher (parent) level to the route level.
Take an example in which code-blocks in the top row (a first code-block line) in a set of two-dimensionally arranged code-blocks are processed from left to right (in the x direction) and, after completion of the processing of the first code-block line, code-blocks in the next row in the y direction (a second code-block line below the first code-block line) are processed. In this case, after the code-block at the left end of the first code-block line is processed, codes in all the parent tag levels of this code-block need to be held until the processing of the code-blocks of the second row is started.
Holding the codes of all the tag levels is not a serious problem as long as the resolution of an image is low. However, in the case of a high resolution image, a large memory capacity is required for holding the codes of all the tag levels, resulting in increasing the cost of an image processing apparatus for processing the image.
If, in order to avoid such a problem, the codes of all the tag levels are loaded into an external memory and reading and writing are performed as needed, processing steps are increased due to frequent access to the external memory, resulting in reducing the overall processing speed. Furthermore, in the case where an LSI is used for performing these operations, the increased number of accesses to the external memory leads to increased power use.
Therefore the codes need to be properly loaded into, for example, a memory that can be accessed at high speed and an external memory having a large capacity according to the progress of the processing of the code-blocks of the image, but such a control technique is not used in the image processing apparatuses of Patent Documents 1 and 2.